1. Field of the Invention
The present invention relates to a solid-state image sensor and particularly to a solid-state image sensor with a charge sweep device (referred to hereinafter as CSD) using Schottky barrier photo sensors.
2. Description of the Prior Art
Among solid-state image sensors, there is known a sensor using a charge sweep device (CSD) for vertical transfer of charge. Such a solid-state image sensor with CSD is described in Technical Digest of ISSCC 85, pp. 100-101 by M. Kimata et al. A solid-state image sensor using a Schottky barrier is described for example by M. Kimata et al. in Japanese Journal of Applied Physics, Vol. 21 (1982), Supplement 21-1,pp. 231-235.
FIG. 1 is a plan view showing an array of a conventional solid-state image sensor with CSD, particularly disclosed in Japanese Patent Laying-Open Gazette No. 68969/1984 (counterpart U.S. Pat. No. 4,581,539). FIG. 1 shows an array of 3 columns.times.4 rows for simplification. In this figure, photo sensors 1 are arrayed in a matrix on a semiconductor substrate. The photo sensors 1 store electric charge according to an amount of received light. A transfer gate 2 is provided for each photo sensor 1 on the semiconductor substrate. The transfer gate 2 controls reading of the charge stored in the associated photo sensor 1. Vertical charge transfer elements 3 are formed on the semiconductor substrate along the column direction of the photo sensors 1. Further, a horizontal charge coupled device (CCD) 5 and interface portions 4 serving as interface between the horizontal CCD 5 and the respective vertical charge transfer elements 3 are formed on the semiconductor substrate. The horizontal CCD 5 is connected with an output preamplifier 6. An output end of the output preamplifier 6 is connected to an output terminal 7.
The horizontal CCD 5 and the output preamplifier 6 in the solid-state image sensor thus constructed may be entirely the same as those in the conventional solid-state image senso of the CCD system. A characteristic feature of the solid-state image sensor shown in FIG. 1 resides in portions related with transfer of charge in the vertical direction, namely, the vertical charge transfer elements 3 and the interface portions 4. Therefore, structure and operation of these portions will be described in the following with reference to FIGS. 2A, 2B and 3.
FIG. 2A is a sectional view taken along the line A-A' in FIG. 1. As shown in FIG. 1, a vertical charge transfer element 3 comprises a layer of high resistance, e.g. a gate electrode 31 formed of polysilicon doped with a small amount of As, and wires 3a to 3d for applying potential to the gate electrode 31. An interface portion 4 comprises two gate electrodes 41 and 42 and an end of the interface portion 4 contacts a gate electrode 51 of the horizontal CCD 5. A channel for transfer of charge is formed under each gate electrode in the semiconductor substrate 8. Those channels may be surface channels or buried channels.
Clock signals .phi.v1 to .phi.v4, .phi.s and .phi.t as shown in FIG. 3 are applied to the gate electrodes 31, 41 and 42, respectively. A clock signal .phi.h is applied to the gate electrode 51. The clock signals .phi.v1 to .phi.v4 are applied to the wires 3a to 3d, respectively. Although the conventional example is assumed to use N channels, P channels may be used by reversing the polarities of the clock signals.
Now, vertical transfer of charge in the portion shown in FIG. 2A will be described with reference to (a) to (i) of FIG. 2B as well as FIG. 3. The states (a) to (i) of FIG. 2B represent potential states of the channels corresponding to the positions shown in FIG. 2A at timing t1 to timing t9, respectively.
The state (a) of FIG. 2B is a potential state corresponding to the timing t1 shown in FIG. 3. In this state, the clock signals .phi.v1 to .phi.v4 are all at a high level and accordingly a large potential well is formed under the gate electrode 31. The clock signal .phi.s is at a level higher than that of the clock signals .phi.v1 to .phi.v4 and consequently a deeper potential well is formed under the gate electrode 41. In addition, the clock signal .phi.t is at a low level and accordingly a shallow potential barrier is formed under the gate electrode 42. On the other hand, the horizontal CCD 5 performs transfer of the charge in this state and changes repeatedly between the potentials as shown by the dotted lines in the FIGURE. When any transfer gate 2 in the vertical direction, namely, in the column direction is conducted to read out the content of the photo sensor 1 onto the vertical charge transfer element 3, it follows that the signal charge Qsig exists in a prescribed position of the gate electrode 31.
Then, if the clock signal .phi.v1 is changed to the low level at the timing t2 shown in FIG. 3, the potential well under the wire 3a becomes shallow and has an inclination from a portion under the wire 3a to a portion under the wire 3b as shown in (b) of FIG. 2B. As a result, the signal charge Qsig extends in space and is pushed toward the direction of the arrow X shown in FIG. 2B.
Subsequently, if the clock signals .phi.v2 to .phi.v4 are successively changed to the low level at t3, t4 and t5 as shown in FIG. 3, the potentials under the wires 3b to 3d are successively changed to the low level as shown in (c) to (e) of FIG. 2B and, accordingly, the potentials under the gate electrode 31 successively become shallow, whereby the inclined portion moves in the direction of the arrow X. Thus, the signal charge Qsig is forced to move toward the direction of the arrow X and when the clock signal .phi.v4 falls to the low level, the signal charge Qsig is stored in the potential well under the gate electrode 41. A current value in the wires (for example, a value of current flowing in the wires 3a and 3b when the wire 3a is at the high level and the wire 3b is at the low level) is determined by the resistance values of the gate electrodes and consumption of electric power depends on the current value. Therefore, the resistance values of the gate electrodes are desirably large values. However, if the resistance values are too large, a potential inclination between the wires 3a and 3b cannot be formed in a good condition when the wire 3b for example changes from the high level to the low level. Accordingly, the resistance value of the gate electrode 31 is preferably 1M.OMEGA./.quadrature. to 1G.OMEGA./.quadrature. (.OMEGA./.quadrature. being a unit of sheet resistance). This value can be obtained if polysilicon for example is formed by a CVD method and is doped with a small amount of arsenic. The gate electrode 41 needs to be sufficiently large for storing the signal charge Qsig, while the potential at the high level of the clock signal .phi.s does not need to be deeper than the potential under the wires 3a to 3d and may be of the same depth as this potential.
Thus, the signal charge Qsig is collected to the gate electrode 41. After scanning for one horizontal line of the horizontal CCD 5, the clock signal .phi.h of the gate electrode 51 of the horizontal CCD 5 in contact with the gate electrode 42 is changed to the high level and the clock signal .phi.t of the gate electrode 42 is also changed to the high level. As a result, the potentials under the respective gate electrodes become as shown in (f) of FIG. 2B. At this time, the potential under the gate electrode 42 is higher than the potential under the gate electrodes 41 and 51. However, it does not need to be higher than the potential under the gate electrodes 41 and 51 and it may be equal thereto.
Subsequently, at the timing t7 shown in FIG. 3, the clock signal .phi.s is changed to the low level and as shown in (g) of FIG. 2B, the potential under the gate electrode 41 becomes shallow. As a result, the signal charge Qsig is moved into the potential well under the gate electrode 51.
After that, at the timing t8 shown in FIG. 3, the clock signal .phi.t is changed to the low level and as shown in (h) of FIG. 2B, the potential under the gate electrode 42 becomes shallow so that the signal charge Qsig is transferred by the horizontal CCD 5. Thus, the horizontal CCD 5 receiving the signal (the signal charge Qsig) successively transfers the signal to the output preamplifier 6.
When the signal is transferred by the CCD 5 as described above, the clock signals .phi.v1 to .phi.v4 and .phi.s are changed again to the high level at the timing t9 shown in FIG. 3 so that the same condition as in the case of the timing t1 is established. Subsequently, the above described sequential cycle is repeated.
Although the above description of the operation of the conventional example is related with reading out of the contents of the photo sensors 1 associated with one vertical charge transfer elements 3, the other vertical charge transfer elements 3 perform simultaneously the same operation as described above. More specifically, the transfer gates 2 are simultaneously selected for each row to read the charge stored in the photo sensor 1 concerned, whereby each vertical charge transfer element 3 transfers the charge simultaneously in the column direction.
Since the photo sensors 1, the vertical charge transfer elements 3 and the transfer gates 2 are formed on the same plane of the semiconductor substrate 8 in the conventional solid-state image sensor with CSD, the conventional image sensor involves a problem that the fill factor (a proportion of the areas of the photo sensors to the areas of picture elements) is still limited by the isolation of the devices, the transfer gates and the CSD channels even if the adoption of the CSD system makes it possible to decrease the channel width of each vertical charge transfer element to a limit value in photolithography. In addition, practically, the width of the CSD channel is limited by a so-called narrow channel effect (a phenomenon in which according to decrease of a channel width, horizontal diffusion of impurity from the adjacent impurity region occurs conspicuously to cause a change in the characteristics of the channel). Therefore, it is practically impossible to reduce the channel width to a limit value in photolithography and an opening proportion larger than a certain value can not be obtained.